The present invention relates to a process for fabricating a semiconductor device having a planarized surface, and more specifically to a process for fabricating a semiconductor device of a trench isolation type semiconductor device in which a device isolation is realized by filling an insulator film into a trench formed in a semiconductor substrate or a semiconductor device having a buried interconnection structure of a conductive material filled up into a trench formed in an interlayer insulator film.
With an increased integration density of the semiconductor device, a device isolation structure has changed from a conventional LOCOS (local oxidation of silicon) type to a trench isolation realized by filling an insulator film into a trench. In particular, recently, in order to further microminiaturize the semiconductor device, the trench isolation structure trends to reduce not only a trench width not also a trench depth. For example, a shallow trench isolation (abbreviated to "STI") having the trench width of 0.2 .mu.m and the trench depth of 0.3 .mu.m has been already reduced into practice.
Furthermore, a semiconductor device having a multi-level interconnection structure has been proposed which has an interconnection formed of a buried interconnection structure of a conductive material filled up into a trench formed in an interlayer insulator film on a semiconductor substrate, in order to planarize a surface (buried interconnection structure).
In the trench isolation structure and the buried interconnection structure, the trench is formed in the semiconductor substrate and in the interlayer insulator film, and the insulator film or the conductive material is filled up into the trench. Thereafter, the insulator film or the conductive material is removed from regions other than the trench by a chemical mechanical polishing (CMP).
Here, this type of technology will be described with reference to an example of the trench isolation structure. First, as shown in FIG. 1A, a silicon oxide film 202 having a thickness of 20 nm is formed on a principal surface of a silicon substrate 201 by means of a thermal oxidation, and a silicon nitride film 203 having a thickness of 150 nm is formed on the silicon oxide film 202 by means of a CVD (chemical vapor deposition) process. Furthermore, a silicon oxide film 204 having a thickness of 10 nm is formed on the silicon nitride film 203 by means of the CVD process.
Thereafter, as shown in FIG. 1B, a photo resist film 205 is formed on the silicon oxide film 204, and then, is selectively removed from a portion of the photo resist film corresponding to a device isolation region to form a patterned photo resist film having an aperture 206. By using the patterned photo resist 205 as a mask, the silicon oxide film 204 and the silicon nitride film 203 are etched to form an opening 207, as shown in FIG. 1C. Furthermore, the photo resist film 205 is removed by means of an ashing. In this ashing process, the silicon oxide film 204 is simultaneously removed.
Then, as shown in FIG. 1D, by using the patterned silicon nitride film 203, the silicon substrate 201 is etched to a desired depth so that a fine and shallow trench (device isolation trench) 208 is formed.
Thereafter, as shown in FIG. 1E, a silicon oxide film 209 formed of a non-doped silicate glass (NSG) which is obtained by decomposing TEOS (tetraethoxysilane) by a LPCVD (low pressure CVD) process, is deposited on the silicon substrate 201 to fill up the trench 208. The non-doped silicate glass (NSG) obtained by decomposing the TEOS will be called a "TEOS NSG" in this specification. Since this TEOS NSG film 209 has a feature that a precursor of the film has a large surface migration, and therefore since the TEOS NSG film has a relatively good step coverage, the TEOS NSG film is very effective in filling up the trench.
Thereafter, as shown in FIG. 1F, the TEOS NSG film 209 and the silicon nitride film 203 are etch-removed by a chemical mechanical polishing (CMP) until a lower portion of the silicon nitride film 203 remains. Furthermore, a surface of the TEOS NSG film 209 is etched to a certain degree so that the level of the surface of the TEOS NSG film 209 is lower than the level of the silicon nitride film 203, as shown in FIG. 1G.
As shown in FIG. 1H, the silicon nitride film 203 is etch-removed by a hydrofluoric acid, and succeedingly, the silicon oxide film 202 is etch-removed by a wet etching. In this process, the surface of the TEOS NSG film 209 is etched to a certain degree, so that the level of the surface of the TEOS NSG film 209 becomes the same as the level of the silicon nitride film 203. Thus, the TEOS NSG film 209 remains in the condition that the TEOS NSG film 209 fills up in only the trench 208. Namely, the STI structure is formed.
In the above mentioned STI structure, however, when the TEOS NSG film 209 is etch-removed by the CMP process, an abrasive agent is applied to a surface of a wafer including a number of silicon substrates 201, and the surface of the wafer is polished. In this polishing process, because of a camber of the wafer and an uneven distribution of a contacting force of the abrasive agent, the polishing amount varies on the surface of the wafer. Generally, as shown in FIG. 2A, the polishing amount in a central region of a silicon wafer W is remarkably larger than the polishing amount in a peripheral region of the silicon wafer W, with the result that a central region of a surface of the silicon wafer W is recessed in comparison with a peripheral region of the surface of the silicon wafer W. Therefore, as shown in FIGS. 2B and 2C which are enlarged diagrammatic sectional views of the peripheral region and the central region of the silicon wafer, for illustrating the condition that the silicon nitride film 203 has been polished by the CMP process, a thickness t.sub.1 of the silicon nitride film 203 remaining in the central region of the silicon wafer W becomes smaller than a thickness t.sub.2 of the silicon nitride film 203 remaining in the peripheral region of the silicon wafer W.
In the condition that the silicon nitride film 203 has a thickness variation caused in the CMP process, if the process is advanced, in the process shown in FIG. 1H, the remaining step X1 occurs as shown in FIG. 2D, because the height of the TEOS NSG film 209 from the principal surface of the silicon substrate 210 in the wafer peripheral region is higher than the height of the TEOS NSG film 209 from the principal surface of the silicon substrate 210 in the wafer central region. On the other hand, in the wafer central region, the etching of the TEOS NSG film 209 exceeds an expected amount, so that as shown in FIG. 2E, a divot X2 occurs at a boundary between the TEOS NSG film 209 filled in the trench 208 and the silicon substrate 210 at the principal surface of the silicon substrate 210. The reason for this is that: because an edge of the TEOS NSG film 209 contacts with an edge of the trench 208 of the silicon substrate 210 which is not etched in the process shown in FIG. 1H, the etching advances from the edge of the edge of the TEOS NSG film 209 into an inside of the trench 208.
If the remaining step X1 or the divot X2 occurs in the silicon substrate, the planarity of the surface of the silicon substrate is deteriorated, with the result that a variation occurs in the size of a gate electrode formed on a silicon substrate in a later step, and therefore, it becomes difficult to fabricate a MOS transistor as designed. Alternatively, an etching residual of a gate electrode material often causes a short-circuit, with the result that the device becomes defective. This problem similarly occurs in forming the buried interconnection structure, because the deterioration of the planarity causes the size variation of an upper level interconnection and a short-circuiting.
Incidentally, in connection with the above mentioned problem, Japanese Patent Application Pre-examination Publication No. JP-A-61-166041 proposes a technology for forming a planar device isolation structure, by using a diamond thin film as a polishing stop thin film, since the diamond thin film has a high mechanical resistance. However, this publication only discloses that a reaction ion etching is used for patterning the diamond thin film into a desired pattern, but the details are not disclosed in connection with a method for forming a mask used for etching the diamond thin film, and a method for removing the mask.
Because of this, according to the disclosure of this publication, the diamond thin film which has the high mechanical resistance but which can be easily removed by an oxygen ashing, is patterned into a desired pattern by use of a pattern photoresist, however, when the photo resist is ashed, the diamond thin film is simultaneously removed by the ashing process. In other words, the disclosure of this publication is difficult to actually use the diamond thin film as the etching stopper in the CMP process.